A metal-oxide-semiconductor field effect transistor (MOSFET) is currently one of the most promising elements applied by a semiconductor device, due to the superior characteristics in view of operating speed and/or power consumption and cost efficiency.
Currently, in order to further enhance the performance of the MOSFET, a strained-Si channel technology, such as utilizing a contact etch stop layer (CESL) with compress/strain stress (referred as stress-inducing CESL), is applied to raise the channel carrier mobility of MOSFETs.
To take a stress-inducing CESL as an example, its formation may comprises following steps: A silicon nitride (SiN) dielectric layer covering on a transistor are firstly provided, and an ultra-violate (UV) curing step is then performed to make the SiN dielectric layer gradually gaining a stress, such that the carrier mobility of the transistor subject to the stress can be improved.
However, the semiconductor device still suffers some problems as each technology nodes shrink and the dimension and element pitch of the semiconductor device are reduced. For example, during the UV curing step, voids or gaps may occur in these aforementioned material layers due to the stress gain and the difference of expansion rate between the different material layers. As a result, some undesired metal leads may occur on the metal lines or plugs generated by a subsequent interconnection process and extend along those voids. At the worst, the semiconductor device may be shortened out by those metal leads.
Therefore, there is a need of providing an advanced method for fabricating a semiconductor device to obviate the drawbacks and problems encountered from the prior art.